The present invention is directed to a correlator and a delay locked loop circuit. More particularly, to a correlator for detecting the code phase of a spreading code on the transmitting side (i.e., the code phase of the received spreading code) in a case where a direct-sequence spread-spectrum signal is received, and to a delay locked loop (DLL) circuit for maintaining the synchronization between the received spreading code and a reference spreading code.
Direct-sequence code division multiple-access based upon direct-sequence spread-spectrum (DS-SS) modulation has been considered as a wireless access scheme for next-generation digital mobile communications systems. In order to receive a spread-spectrum signal, the code phase of the spreading code on the transmitting side must be detected on the receiving side and a spreading code for despreading purposes must be generated so as to achieve phase synchronization with the spreading code on the transmitting side.
Digital cellular wireless communication systems using DS-CDMA (Direct-Sequence Code Division Multiple-Access) technology have been developed as next-generation mobile communication systems for implementing wireless multimedia communications. In a CDMA digital cellular wireless communications system of this kind, a base station transmits control information and user information after multiplying this information with a spreading code. Individual mobile stations spread and transmit information using a spreading code specified by the base station. In order for a mobile station to correctly receive information such as control information from the base station in a CDMA digital cellular wireless communications system of this kind, it is necessary to identify the timing at which the spread-spectrum modulation starts at the base station, i.e., the phase of the spreading code.
FIG. 19 shows a receiver of a mobile station for a CDMA digital cellular wireless communication system. The receiver includes an antenna 1, a receiver circuit 2 for performing amplification and frequency conversion from RF (radio frequency) to IF (intermediate frequency), a QPSK detector 3 for performing QPSK detection and outputting I, Q signals and an A/D converter 4 for converting baseband analog I, Q signals output from detector 3 to digital I, Q data, a despreading circuit 5 for applying despread processing to the I, Q data output by the A/D converter 4, a data demodulator 6 for performing synchronous detection, data discrimination and error correction, a correlator 7 for performing a correlation operation in order to identify spread start timing (the phase of the received spreading code) and a timing decision unit 8 for identifying spread start timing (phase) from correlation value.
The correlator 7 performs a correlation operation between a received spread-spectrum data sequence and a reference spreading code sequence (a spreading code sequence identical with that on the side of the base station).
As shown in FIG. 20, a spreader 9 on a transmitting side executes spread processing and transmits a signal indicated by:X(t)=a(t)·c(t)
Where a(t) represents transmitted data and c(t) a PN (pseudorandom number) sequence.
The PN sequence c(t) is a spreading code sequence of “1”s and “0”s. The same code sequence (a code sequence of N chips) is repeated on a per-symbol basis, wherein one symbol corresponds to one-bit of data.
The signal x(t) is received on the receiving side, where the correlator 7 calculates the correlation between the signal x(t) and a reference spreading code c(t−τ) and outputs a correlation value R(t) indicated by the following equation:
                              R          ⁡                      (            t            )                          =                ⁢                  Σ          ⁢                                          ⁢                                    x              ⁡                              (                t                )                                      ·                          c              ⁡                              (                                  t                  -                  τ                                )                                                                                      =                    ⁢                      Σ            ⁢                                                  ⁢                                          a                ⁡                                  (                  t                  )                                            ·                              c                ⁡                                  (                  t                  )                                            ·                              c                ⁡                                  (                                      t                    -                    τ                                    )                                                                    ,                  t          =          Tc                ,                  2          ⁢          Tc                ,                  ⋯          ⁢                                          ⁢                      N            ·            Tc                              where τ represents a code shift (phase difference) between the spreading code on the transmitting side and the reference spreading code of the correlator on the receiving side. The integration interval is the duration of one symbol (the time period of N chips, which is equal to N·Tc).
If “a(t)=1” holds in the above equation, the correlation value R(t) will indicate the auto correlation value of the PN sequence. If the PN sequence is an M sequence, R(t)=N (1 when normalized) is obtained as a maximum at τ=0 and R(t)=1/N holds at τ≠0. In actuality, a(t) is unknown and may be “1” or “0”. However, by assuming for example that “1”=−1 and “0”1, and integrating the absolute value of a(t)·c(t)·c(t−τ), R(t)=1 is obtained at τ=0 and R(t)=1/N at τ≠0.
Thus, by calculating correlation values while changing the phase of the reference spreading code c(t−τ) one chip width Tc at a time and detecting the timing at which the correlation value exceeds a set level, it is possible to identify the spread start timing on the transmitting side (the phase of the spreading code on the transmitting side). Accordingly, the timing decision unit 8 of FIG. 19 acquires the spread start timing (phase) based upon the timing at which the correlation value output by the correlator 7 exceeds the set level and inputs this timing to the despreader circuit 5.
A matched filter and a sliding correlator are available as the principal correlation detection techniques applied to DS-SS signals.
FIG. 21 shows a matched filter 71. The matched filter includes an N-chip shift register (s1–sN) 71a for successively shifting the received spread-spectrum data sequence of the baseband (the output of the A/D converter in FIG. 19) at the chip frequency. Also included is an N-chip shift register (c1–cN) 71b for storing the reference spreading code sequence, N-number of multiplying corresponding bits of the baseband spread-spectrum data sequence and reference spreading code sequence. An adder circuit 71d is further included for adding the outputs of the multipliers and a PN generator 71e for generating the PN sequence (the reference spreading code sequence).
The reference spreading code sequence is composed of N chips. The matched filter 71 outputs one correlation value R(t) per chip period Tc and then successively outputs a correlation value every time the phase of the baseband spread-spectrum data sequence changes by one chip width Tc. The matched filter thus outputs correlation values of N-number of different phases over the period of one symbol.
The timing decision unit 8 monitors the correlation value R(t) output by the matched filter 71, determines whether the correlation value has exceeded the set level and identifies the start of the spreading code sequence on the transmitting side (spread start timing) when the correlation value exceeds the set level.
FIG. 22 shows a sliding correlator 72, which includes a PN generator 72a for generating a PN sequence (reference spreading code sequence). The reference spreading code sequence is composed of N chips and is generated cyclically at the symbol period T (=N×Tc). Further, multiplier 72b multiples the baseband spread-spectrum data sequence (the received signal) by the reference spreading code sequence chip by chip and outputs the result.
An integrator 72c integrates N chips of the output of multiplier 72b and outputs the correlation value R(t). The integrator 72c includes an adder 73 for adding the output of the multiplier 72b and the current integrated value, and a delay circuit 74 for outputting the integrated value from adder 73 upon delaying the value by one chip period.
The sliding correlator 72 outputs one correlation value R(t) in one symbol period (the period of N chips) and shifts the phase of the reference spreading code by one chip every symbol, thereby outputting correlation values of N-number of different phases over the period of N symbols (=N2·Tc).
The timing decision unit 8 monitors the correlation value R(t) output by the sliding correlator 72 to determine whether the correlation value has exceeded the set level. Further, the timing decision unit shifts the phase of the reference spreading code if the correlation value is less than the set level and identifies the start of the spreading code sequence on the transmitting side when the correlation value exceeds the set level.
Thus, the phase of the spreading code on the transmitting side can be detected at a precision of within one chip by the matched filter or sliding correlator. (This is referred to as “synchronization acquisition”.) This is followed by performing despreading by generating the spreading code sequence in sync with the detected phase to despread on the receiving side.
However, if no further action is taken once synchronization has been acquired, the synchronizing position will be lost owing to the effects of modulation and noise. This makes it necessary to exercise control in such a manner that the spreading code sequence on the receiving side will not develop a time shift with respect to a received signal for which synchronization has been acquired. (This is referred to as “synchronization tracking”.) A DLL (Delay Locked Loop) is known as such a synchronization tracking circuit.
FIG. 23 shows a DLL circuit, which includes a PN generator 9a that generates a first PN sequence (the reference spreading code). The PN generator 9a has nine delay circuits D1–D9 and an Ex-OR gate provided at the input of the fourth delay circuit. This configuration outputs a PN sequence of an M sequence in accordance with X9+X4+1. The first PN sequence A1 is composed of N chips (=29=512) and is generated cyclically at the symbol period T (=N×Tc).
A delay circuit 9b delays the first PN sequence (reference spreading code) A1 by one chip and outputs a second PN sequence A2. A multiplier 9c multiplies, chip by chip, the first PN sequence A1 output by the PN generator 9a and a received spread-spectrum data sequence B. A multiplier 9d multiplies, chip by chip, the second PN sequence A2 delayed by one chip and the received spread-spectrum data sequence B.
Further, an adder 9e adds the output of the multiplier 9c and a signal obtained by inverting the code output by the multiplier 9d. The output of the adder 9e is input to a low-pass filter 9f, the output whereof is applied to a voltage-controlled oscillator (VCO) 9g, which varies the clock frequency (chip frequency) based upon the output of the low-pass filter.
The multiplier 9c and low-pass filter 9f function to calculate the correlation between the first PN sequence A1 and the received spread-spectrum data sequence B. If the phase of the first PN sequence and the phase of the received spread-spectrum data sequence match, the maximum output is obtained.
As shown in (a) of FIG. 24, a correlation value R(τ)=1 having the width of one chip is output every symbol. If the phase shifts by the width of one chip or more, the correlation value R(τ) becomes 1/N.
The multiplier 9d and low-pass filter 9f function to calculate the correlation between the second PN sequence A2 delayed by one chip width and the received spread-spectrum data sequence B. If the phase of the second PN sequence and the phase of the received spread-spectrum data sequence match, the maximum output is obtained and a correlation value R(τ) is output, as shown in (b) of FIG. 24. If the phase shifts by the width of one chip or more, the correlation value R(τ) becomes 1/N. The adder 9e adds the output of the multiplier 9c and a signal obtained by inverting the output of the multiplier 9d. As a result, a signal having an S-curve characteristic shown in (c) of FIG. 24 with respect to a phase difference τ is output via the low-pass filter 9f. 
On the basis of the output of the low-pass filter, the voltage-controlled oscillator 9g controls the clock frequency in such a manner that the phase difference τ becomes zero. For example, if the phase of the PN sequence (reference spreading code) leads that of the received spreading code, control is performed so as to make the phase difference zero by lowering the clock frequency. If the phase of the PN sequence (reference spreading code) lags behind that of the received spreading code, control is performed so as to make the phase difference zero by raising the clock frequency.
Thus, the phase of the spreading code sequence on the transmitting side is detected (synchronization acquisition) at a precision of within one chip by the correlator (the matched filter of FIG. 21 or sliding correlator of FIG. 22), and then synchronization tracking is carried out by the DLL circuit.
FIG. 25 shows another example of a DLL circuit. In particular, FIG. 25a shows a DLL circuit having a configuration similar to FIG. 23. FIG. 25(b) shows a configuration of another DLL circuit obtained by modifying the DLL circuit of FIG. 25(a). Since multiplication by the PN code and adding the results of multiplication are linear operations, the operations can be interchanged in terms of their order. Accordingly, the DLL circuit of FIG. 25a provides an equivalent function even if the adjacent first and second PN code sequences are multiplied by +1 and −1 by multipliers 9h, 9I, respectively. Further, the products are added by an adder 9j and the received signal is multiplied by the value of the sum, as shown in FIG. 25(b).
The time needed to detect a code phase, the scale of the circuitry and the power consumption associated with the matched filter are compared with those associated with the sliding correlator, the following results are obtained:
(1) If the code length for obtaining correlation is N chips, the code phase detection time required for initial synchronization of reception will be N chips (=N·Tc) in case of the matched filter and N2 chips (=N2·Tc) in case of the sliding correlator. In other words, the matched filter requires less time to detect the code phase, namely 1/N of the time required in case of the sliding correlator.
(2) The scale of the circuitry in a case where the correlator is implemented by digital processing is understood from FIGS. 21 and 22. Specifically, the matched filter requires two shift registers each having a length equivalent to the number of taps (=N), multipliers equivalent to the number of taps and one cumulative adder. The sliding correlator, on the other hand, requires only one multiplier and one cumulative adder. Therefore, the scale of the hardware of the matched filter is much greater than that of the sliding correlator.
(3) The power consumption of the circuitry is considered to be proportional to the product of the number of gates used and the operating frequency based on the assumption that CMOS LSI circuitry is used. The operating frequency is the chip frequency or the over-sampling frequency of the chip in the case of both the matched filter and sliding correlator. Power consumption, therefore, is considered to be proportional to the scale of the circuitry. Accordingly, the power consumed by the matched filter is much greater than that by the sliding correlator.
Although the matched filter is advantageous in that code phase detection time is short, the scale of the circuitry is very large. A problem that arises, therefore, is that a matched filter cannot be used in a mobile station, which requires low power consumption. The sliding correlator, on the other hand, has the advantage of small-scale circuitry. However, since code phase detection time is long, achieving initial synchronization in the demodulation operation takes time which causes degradation of the system characteristics.
Further, with the conventional DLL circuit, the phase synchronization acquisition range (i.e., the lock range) is small, namely the width of one chip or −Tc/2 to Tc/2, as is evident from FIG. 24(c). However, a problem that arises is that synchronization tracking can no longer be performed if a phase shift in excess of one chip occurs.